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FPGA Design Services 

In the last 15 years the FPGA technology had an explosion in popularity and capabilties. If a few years ago a one million gates FPGA was considered a large device, today is almost a middle-range device. All in all, FPGA is a technology that allows you to have complex functionality in a small space. Hardware TCP/IP, MAC, UDP, Hardcoded and SoftCoded microprocessors, 10G and 40G SerDes, Hardcoded 1G and 10G MAC has made of this technology a must have option. We have experience designing several complex IP, some of which takes almost one million gates to implement. It is almost impossible to think, these days, of having something really advanced without a FPGA inside. 

Some of our IP Designed

  • SHD/SONET Framer/ Deframer
  • ATM/ALLx Switch
  • 1G/10G Ethernet MAC
  • 1G/10G UDP/IP stack
  • Porting ucLinux to Xilinx FPGA
  • Redesign of obsolete ICs.

FPGA Design Process

Design Specification given to us from our customer, for example in the CASE STUDY above is "design a chip that works like this one"

Feasibility Study in which we select the FPGA of the right size and package for the requested job.

VHDL Coding FPGA can be programmed just like any Computer program, VHDL is the most common language used to program FPGA in Europe.

Simulation for the FPGA needs to be simulated with program like ModelSim, Active-HDL or ISim
Verification on hardware systems

Documentation we provide a datasheet for the IP designed or for the whole IC.

A Note about Code Coverage

By F. Poderico

Code coverage is a technology used to understand which part of your code has not been tested. Mentro graphic, was probably the first company to understand this key aspect of a design. In applications where the FPGA can't be replaced (for example Space application) the code coverage is a requirement from the European Space Agency and it should be mandatory for every critical design when things just can't go wrong. When running a simulation with the code coverage on the simulator checks which part of the code has not been tested, or even which part of a switch statement has not been simulated. This minimizes the number of bugs, improves the verification and is a good indicator to rank your simulation stimulus.
Unfortunately it is impossible to have a coverage of 100% for any design, and the reason are pratical, time requirement, budget, impossibility to create simulation vector for a given design.
For more information on code coverage check this article


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